aurora_topFloorplan
DEMO-45Routed reference design1,100 objects
TOPXY
DESIGN OVERVIEW
control_unit/ elaborated logic
Click an input to toggle · Drag gates to arrange · Click an output pin, then an input pin to connect
control_unit.vVERILOG
Ln 1, Col 1UTF-8Spaces: 4Combinational subset · 1–32 bit unsigned signals
Two-state combinational simulationUnit sample interval · no analog timing model
Cursor: 0Click a waveform to inspect signal values